<?xml version="1.0"?> <model xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <bank bar="0" size="0x0200" protocol="software_registers" read_address="0x9000" write_address="0x9000" word_size="32" endianess="little" format="0x%lx" name="fpga" description="IPECamera Registers"> <register address="0x00" offset="0" size="32" default="0" rwmask="0" mode="RW" name="spi_conf_input"/> <register address="0x10" offset="0" size="32" default="0" rwmask="0" mode="R" name="spi_conf_output"/> <register address="0x20" offset="0" size="32" default="0" rwmask="0" mode="RW" name="spi_clk_speed"/> <register address="0x30" offset="0" size="32" default="0" rwmask="0" mode="R" name="firmware_info"> <field offset="0" size="8" mode="R" name="firmware_version"/> <field offset="8" size="1" mode="R" name="firmware_bitmode"/> <field offset="12" size="2" mode="R" name="adc_resolution"/> <field offset="16" size="2" mode="R" name="output_mode"/> </register> <register address="0x40" offset="0" size="32" default="0" rwmask="0" mode="RW" name="control"> <field offset="31" size="1" mode="R" name="freq"/> </register> <register address="0x50" offset="0" size="32" default="0" rwmask="0" mode="R" name="status"/> <register address="0x54" offset="0" size="32" default="0" rwmask="0" mode="R" name="status2"/> <register address="0x58" offset="0" size="32" default="0" rwmask="0" mode="R" name="status3"/> <register address="0x5c" offset="0" size="32" default="0" rwmask="0" mode="R" name="fr_status"/> <register address="0x70" offset="0" size="32" default="0" rwmask="0" mode="R" name="start_address"/> <register address="0x74" offset="0" size="32" default="0" rwmask="0" mode="R" name="end_address"/> <register address="0x78" offset="0" size="32" default="0" rwmask="0" mode="R" name="rd_address"/> <register address="0xa0" offset="0" size="32" default="0" rwmask="0" mode="R" name="fr_param1"> <field offset="0" size="10" mode="RW" name="fr_skip_lines"/> <field offset="10" size="11" mode="RW" name="fr_num_lines"/> <field offset="21" size="11" mode="RW" name="fr_start_address"/> </register> <register address="0xb0" offset="0" size="32" default="0" rwmask="all" mode="RW" name="fr_param2"> <field offset="0" size="11" mode="RW" name="fr_threshold_start_line"/> <field offset="16" size="10" mode="RW" name="fr_area_lines"/> </register> <register address="0xc0" offset="0" size="32" default="0" rwmask="0" mode="R" name="skiped_lines"/> <register address="0xd0" offset="0" size="32" default="0" rwmask="all" mode="RW" name="fr_thresholds"/> <register address="0xd0" offset="0" size="10" default="0" rwmask="all" mode="RW" name="fr_pixel_thr"/> <register address="0xd0" offset="10" size="11" default="0" rwmask="all" mode="RW" name="fr_num_pixel_thr"/> <register address="0xd0" offset="21" size="11" default="0" rwmask="all" mode="RW" name="fr_num_lines_thr"/> <register address="0x100" offset="0" size="32" default="0" rwmask="0" mode="RW" name="rawdata_pkt_addr"/> <register address="0x110" offset="0" size="32" default="0" rwmask="0" mode="R" name="temperature_info"> <field offset="0" size="16" mode="RW" name="sensor_temperature" min="5" max="15"><view view="formuu1"/><view view="formuu2"/><view view="enumm2"/></field> <field offset="16" size="3" mode="R" name="sensor_temperature_alarms"/> <field offset="19" size="10" mode="RW" name="fpga_temperature"><view view="formuu1"/><view view="enumm1"/></field> <field offset="29" size="3" mode="R" name="fpga_temperature_alarms"/> </register> <register address="0x120" offset="0" size="32" default="0" rwmask="0" mode="R" name="num_lines"/> <register address="0x130" offset="0" size="32" default="0" rwmask="0" mode="R" name="start_line"/> <register address="0x140" offset="0" size="32" default="0" rwmask="0" mode="R" name="exp_time"/> <register address="0x150" offset="0" size="32" default="0" rwmask="0" mode="RW" name="motor"> <field offset="0" size="5" mode="RW" name="motor_phi"/> <field offset="5" size="5" mode="RW" name="motor_z"/> <field offset="10" size="5" mode="RW" name="motor_y"/> <field offset="15" size="5" mode="RW" name="motor_x"/> <field offset="20" size="8" mode="R" name="adc_gain"/> </register> <register address="0x160" offset="0" size="32" default="0" rwmask="0" mode="R" name="write_status"/> <register address="0x170" offset="0" size="32" default="0" rwmask="0" mode="RW" name="num_triggers"/> <register address="0x180" offset="0" size="32" default="0x280" rwmask="0" mode="RW" name="trigger_period"><view view="enumm2"/></register> <register address="0x190" offset="0" size="32" default="0" rwmask="0" mode="R" name="temperature_sample_period"/> <register address="0x1a0" offset="0" size="32" default="0x64" rwmask="0" mode="RW" name="ddr_max_frames"/> <register address="0x1b0" offset="0" size="32" default="0" rwmask="0" mode="R" name="ddr_num_frames"/> </bank> </model>